In prior art systems dynamic RAM arrays are provided with an error correction capability and also with the capability of having the information bits stored in the array periodically refreshed. Each bit location on the chip stores digital information in the form of a "one" or a "zero" as represented by the presence or absence of a quantity of charge stored upon the capacitive element forming a bit. Because there is a tendency over time for a charge which is present to be lost, it is necessary to periodically read the information stored at each bit position of a row of a chip and to write the information back into each bit of the row in order to restore the charge to its initial value. This operation, which is termed a refresh operation, is caused to occur sufficiently frequently that the charge corresponding to a zero or a one is maintained at each bit location near the charge levels to which the bit was charged when the one or zero was originally read in.
The refresh procedure is implemented on a row of a chip by providing to the chip a row address and a row address strobe signal. The strobe signal causes the binary information stored at each column position along the addressed row to be read out by amplifiers connected to each column. The column amplifiers write back into bits of the corresponding addressed row the binary information, either a one or a zero, which was originally stored in that row at each column.
Each row of the chip is sequentially refreshed in the same manner by causing the row address to be incremented by one after each refresh procedure. After the last row of the chip has been refreshed the row address is returned to the first row of the chip and the process of refreshing the rows continues. As stated previously the time duration between successive refresh operations is determined by the total number of rows in the chip and the rate at which the stored charge is lost.
In the prior art if, in spite of refresh, an error existed in a word stored in memory, the existence of the error was not determined until such time as that particular word was requested by a requestor, e.g., a central processor unit (CPU) or an input/output (I/O) device. Errors which occur in bit positions of a word are believed to be caused by alpha particles contained in the atmosphere or within the material from which the RAM array is constructed or perhaps from marginal circuit components. Only at the time that a word is read out of memory pursuant to a request by the requestor is the existence of an error in the word ascertained. If such an error existed in a stored word, the error would be corrected before providing the stored word to the requestor, and the corrected word would also be provided to the memory "write" circuitry in order to write the corrected word back into the same word location. The existence of an error in the word is normally determined by having the memory store extra check bits for each word from which an error in any one of the word bits could be determined. The prior art system has several disadvantages.
One disadvantage is that the requestor may not request a word from a particular location in the memory for a relatively long period of time, the period of time being sufficient that the selected word may experience an error in more than one bit. Thus, a word may not be called from memory for perhaps as long a time as an hour, thereby creating an unnecessarily high probability of an uncorrectable double bit error in that word location before correction would be attempted. Typical error correction techniques have a characteristic that they are capable of correcting single bit errors but if multiple bit errors occur in the word prior to correction of the first bit, the error correction circuitry will detect the presence of multi-bit errors but will be incapable of correcting the multi-bit error condition and the data processing system will incur a malfunction.
There is also a further disadvantage generated by the frequent request for a word from memory where the error may be a "hard" error, i.e., an error which cannot be corrected in memory by writing back the corrected word via the error correction circuitry. A hard error may occur because of a malfunction of a circuit component or, perhaps, a defective bit in memory (e.g., a "stuck-at-zero" or a "stuck-at-one" condition of a bit of memory). In that event, if that word having a hard error is accessed frequently the error correction circuitry will attempt to make a correction into memory each time the word is accessed and will be unsuccessful in making this correction. As a consequence, if a hard error occurs in a word which is frequently accessed, a considerable slowdown in the operation of the machine will occur because of the time required for each error correction attempted.